(A) hybrid buffer design with STT-RAM in large-scale network

Abstract

As interconnection networks proliferate a broad range of high-performance systems, network delay has been a signicant bottleneck in these systems. Using Spin-Transfer Torque RAM(STT-RAM) in input buffers help to alleviate the bottleneck because of its nature of high density. Furthermore, STT-RAM has zero leakage power consumption from memory cell, considerably eliminating standby leakage power. However, deploying STT-RAM is challenging because it has high write latency and write energy consumption.We propose a novel input buffer design of a router in interconnection networks using both SRAM and STT-RAM. In particular, we partition STT-RAM into multiple bank to hide the long write latency. And, we lower the retention time of STT-RAM to reduce its long write latency and its high write energy. Considering that reducing retention time leads to the correctness issues, we present a low-cost ECC-based solution, which adds ECC for old its and shares ECC among different flits. Evaluation shows that the proposed architecture enhances the throughput by 46 % on average, and achieves energy reduction of 30 %.