Investigation of Characteristics in Vertical Si Pillar-type FET with Asymmetric Source and Drain Resistances

Abstract

In this thesis, the transfer characteristics and low-frequency noise (LFN) as well as single transistor latch (STL) were investigated in a vertical Si pillar-type FET. The source resistance ($R_S$) and the drain resistance are inevitably different by reason of ion-implantation and metal contact process due to a vertical configuration. A forward mode (FM) and reverse mode (RM) of voltage sweep were employed by exchanging the source and the drain electrode. The drain current ($I_D$) was higher in the RM than the FM, due to relatively small $R_S$. In case of LFN, the effect of correlated mobility (CMF) was higher in the RM as well as the power spectral density of resistance fluctuation ($S_{RSD}$) was lower than that in the FM. In addition, $R_S$ was very well correlated with the $S_{RSD}$, which indicated that RS severely influence on the $S_{RSD}$. It is imperative to minimize the $R_S$ to suppress $S_{RSD}$. The STL and associated hysteresis was observed only in the RM. On the other hand, hysteresis was not observed in the FM despite STL occurred. The doping concentration at the source node should be high enough so that the generated holes do not escape. In addition, the window of latch voltage ($ΔV_L$) was affected by the series resistance.