DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Lee, Sang-Gug | - |
dc.contributor.advisor | 이상국 | - |
dc.contributor.author | Kim, Keun-Mok | - |
dc.date.accessioned | 2019-09-04T02:43:28Z | - |
dc.date.available | 2019-09-04T02:43:28Z | - |
dc.date.issued | 2018 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=734197&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/266878 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2018.2,[v, 32 p. :] | - |
dc.description.abstract | This thesis presents two types of ultra-low power CMOS logarithmic power detectors with a 65nm CMOS process. Each proposed power detector consists of a rectifier and a logarithmic circuit. MOS transistors at both rectifiers all operate in the sub-threshold region. The logarithmic circuit of the first proposed power detector follows a conventional feedback type, and the second proposed power detector is implemented with a sub-threshold operating MOS transistor load, which is newly suggested in this thesis. The active areas of power detectors are $125 \mu m \times 40 \mu m$ and $60 \mu m \times 55 \mu m$. The proposed power detectors consume $8.11 \mu W and 0.2 \mu W$, respectively, under a 0.6V supply, and dynamic ranges are 41 dB and 21 dB, respectively, with $\pm$ 1 dB error at 915MHz. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | CMOS▼apower detector▼areceived signal strength indicator (RSSI)▼alogarithmic circuit▼aultra-low power▼awireless sensor networks (WSNs) | - |
dc.subject | 상보성 금속 산화막 반도체▼a전력 검출기▼a입력 신호 세기 측정 장치▼a로그 회로▼a초저전력▼a무선센서 네트워크 | - |
dc.title | (An) ultra-low power logarithmic power detector | - |
dc.title.alternative | 초-저전력 로그 전력 검출기 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | 김근목 | - |
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