Adaptive impedance-compensation linearizer for improving power efficiency and signal distortion of a 60 GHz CMOS power amplifier60 GHz CMOS 전력증폭기의 전력 효율 및 신호 왜곡 개선을 위한 적응형 임피던스 보상 선형화 회로

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As the demand for high-speed communication increases, a millimeter-wave radio system with a data rate of Gb/s is required to achieve a high data transmission rate and a low latency. Especially, 60GHz wireless communication has been being introduced to be suitable for Gb/s wireless system due to the wide frequency band of 57~66GHz composed of four channels with a channel bandwidth of 1.76GHz each. Thus, 60GHz-wireless system are being used in a variety of applications requiring high speed and low latency, such as wireless displays, wireless VR / AR HMDs and high speed NFC. However, the 60 GHz frequency band has high oxygen absorption and high free space path loss (FSPL). Also, a receiver with wide channel bandwidth requires more signal-to-noise ratio (SNR). Therefore, to overcome these degradations, a power amplifier with high output power of the TX system is essential. In addition, a high QAM modulation scheme is generally used to increase the data rate of a wireless system. Such a high QAM modulation scheme requires a low error vector magnitude (EVM) to satisfy the SNR required by the overall system rink. Therefore, a high linear power amplifier with low signal distortion is required to implement a high QAM modulation scheme. Therefore, in this paper, we proposed the Adaptive Impedance Compensation Linearizer (AICL), which can improve the linearity, power efficiency and signal distortion of the proposed CMOS PA simultaneously. Thus, a 60-GHz 1-way CMOS power amplifier using the proposed AICL was designed and proposed PA has $0.16mm^2$ of chip size. The simulated peak gain of proposed PA where the linearizer-on, was 22.0 dB, which has 2dB loss compared to case of the linearizer-off. And 3-dB bandwidth of proposed PA has 18 GHz of 54.4~72.4 GHz, and simulated S11 and S22 were satisfied to under -10dB at overall operation frequencies (57~66 GHz). The simulated peak OP1dB and peak PAE at P1dB of proposed PA where the linearizer-on, were 13.0dBm and 17.1%, which increased 3.1dBm and 7.2% respectively compared to case of the linearizer-off. In addition, the simulated peak AM-AM at IP1dBLin.on-6dB and peak AM-PM distortion at IP1dBLin.on of proposed PA, were 0.1dB and -1.7 degree, which improved by 0.7dB and 3.1 degree respectively compared to case of the linearizer-off. Furthermore, the simulated IMD3 and ACPR of proposed PA where 3dBm Pout, were and -40.7 dBc and -52.7dBc, which improved by 7.6 dBc and 8.4 dBc respectively compared to case of the linearizer-off.
Advisors
Park, Chul Soonresearcher박철순researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2019
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2019.2,[vi, 51 p. :]

Keywords

60GHz▼aCMOS▼aPower Amplifier▼aEVM▼aAICL▼aOP1dB▼aPAE▼aAM-AM distortion▼aAM-PM distortion; 60GHz▼aCMOS▼a전력증폭기▼aEVM▼aAICL▼aOP1dB▼aPAE▼aAM-AM 왜곡▼aAM-PM 왜곡

URI
http://hdl.handle.net/10203/266796
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=843425&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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