Terahertz monolithic imagers adopting a VCO-based signal processing

Abstract

In this dissertation, MOSFET characteristics for terahertz (THz) detector application is analyzed to predict the THz responsivity, and is verified by SPICE simulation and 300 GHz on-wafer measurement. The analysis of THz responsivity and noise equivalent power (NEP) depending on the channel dimension and source/drain junction area of the MOSFET detector as well as on the frequency can provide a useful reference for the design of THz detectors. Also, a new architecture of THz imager adopting a VCO-based signal processing is proposed, and 0.5/1.5 THz array imagers are implemented in a 65 nm CMOS. The proposed THz imager architecture presents high signal-to-noise ratio performance, which results in about hundred times enhanced NEP and noise equivalent temperature difference (NETD) compare to previously reported THz imagers. Consequently, a high resolution THz image is obtained by monolithically implemented imager without requiring any external highly sensitive equipment.