First-principles semiconductor interface modeling for atomistic device simulations

Abstract

With the continuous downscaling of Si-based field effect transistors (FETs), the number of atoms in critical dimensions of such small devices becomes countable. In this regime, the role of the gate dielectric layer has become an issue of great importance. The quantum confinement energy and charge distributions in the channel region are considerably affected by the gate dielectric layer and the wave function penetration into oxide may influence the channel/oxide interfacial characteristics. In particular, the interface stress inevitably generated during gate oxidation gives substantial influences on the electronic properties and has emerged as a dominant effect in the atomistic regime. In this thesis, the overall effects of the gate dielectric layers on the performance of Si ultra-thin-body (UTB) FETs have been intensively investigated based on the first-principles density functional theory (DFT). With various SiO2 structural phases, the atomic models of Si/SiO2 structure are realized by using DFT calculations and those effects on the transport properties are examined through full quantum mechanical non-equilibrium Green's function formalism. Moreover, the influence of interface stress effects on the UTB device performance is evaluated by the model calculations, where the efficient device simulations become enabled with the reduced computational cost. The overall results provide significant insight into the importance of considering a gate dielectric layer for the accurate prediction of the performance in nano-scale devices.