Energy efficient DRAM interface through data encoding and security enhancement

Abstract

DRAM, used as a main memory in various modern systems such as mobile, server, IOT, personal computer, systems, consumes a large amount of energy. DRAM is built with a unique cell process to lower the cost per unit capacity and thus is made of a separate chip from the processor. The off-chip interface consumes a lot of energy and power during data transfer because of its large capacitance and its termination to prevent data distortion. As DRAM data rates increase and the use of data-centric applications (i.e., graphics, neural networks) grows, DRAM interfaces are expected to consume more energy in the future. Therefore, to meet the trend of modern computing systems requiring low energy consumption, there needs a way to reduce the energy consumed in the DRAM interface. This thesis deals with two topics related to DRAM interface energy reduction. The first theme is to reduce the energy at the DRAM interface by utilizing the characteristics of the data transferred between the processor and the DRAM. The second theme is a defense mechanism that protects the DRAM from physical attacks with negligible energy consumption at the DRAM interface. A more detailed description of each topic follows. 1. Coding Method Exploiting a Characteristic of Data: To reduce the energy consumed by the off-chip interface, the industry is striving to lower the interface voltage. However, since the interface voltage is already quite small (LPDDR4: 1.1 V), it is difficult to reduce energy by lowering the interface voltage further. Therefore, this paper discusses ways to reduce the energy consumed by DRAM interfaces in different directions from the industry. A key observation of this paper is that the energy consumption of modern DRAM interfaces is not always constant and depends on the data being transmitted. Based on this observation, this paper proposes to transmit optimized data patterns through the DRAM interface regarding energy consumption. Modern DRAM interfaces introduce asymmetric termination to reduce power consumption. In the conventional termination, a termination resistor is connected between the data bus and VDD, and between the data bus and VSS, so that a current path is formed between VDD and VSS to consume energy regardless of data. In the asymmetric termination, however, energy consumption is determined by whether the transmitted data is 0 or 1. Specifically, a termination scheme called 'Pseudo Open Drain' applied to DDR4 and GDDR 4/5 has a termination resistor only between a data bus and VDD, so that a current path is formed (consuming energy) only when 0 is transmitted. The termination scheme called 'Low Voltage Swing Terminated Logic' applied to LPDDR4 has a termination resistor only between a data bus and VSS, and a current path is formed (consuming energy) only when 1 is transmitted. Under this asymmetric termination environment, energy consumption is minimized when the distribution of data is biased to one of zero or one. Based on this observation, this paper discusses ways to reduce interface energy in two ways as follow. As a result of observing the data transmitted through the DRAM data bus, it was confirmed that similar data patterns are repeatedly transmitted. This paper proposes a method to reduce the energy consumed in the DRAM interface by biasing the distribution of data to zero by utilizing the similarity of these data. Specifically, the encoding scheme called Bitwise Difference Encoding (BD-encoding) proposed in this paper transmits the bitwise difference (XOR operation result) between the data to be transmitted and the recently transmitted data (most similar to the data to be transmitted). The more similar the data that is currently transmitted and the data that is recently transmitted, the more biased the distribution of the data, so that a small amount of energy is consumed at the interface. In this paper, we propose to insert encoder and decoder on both sides of memory controller and DRAM. The proposed encoder/decoder module includes a data table and stores data recently transmitted through an interface. At the time of data transmission, the transmitter first finds the data most similar to the data to be transmitted in the table, and then simultaneously transmits the encoded data and the index of the table. The receiver reads the data stored in the data table indicated by the received table index and decodes the data through the bitwise XOR operation. 2. DRAM Physical Defense Mechanism with Negligible Interface Energy: Cold Boot Attack is an attack method that utilizes DRAM remanence feature that data stored in DRAM does not disappear even after power is turned off at low temperature. In detail, during the cold boot attack, the attacker freezes the DRAM module, 2) detaches the module from the system, 3) moves the DRAM module to its own system, and 4) reads the information stored in the DRAM. In this way, the attacker steals the security keys stored in the DRAM, recent e-mails, photos, and visited web sites. Memory data encryption is a typical method for completely protecting information stored in the DRAM from a cold boot attack. In this method, the memory controller stores the encrypted information in the DRAM and decrypts it when reading the data. Therefore, even though an attacker steals data stored in DRAM through a cold boot attack, he cannot get the meaningful information because he cannot decrypt it. However, this method must generate a security key through the cipher engine whenever data is written to or read from the DRAM. Complicated security key generation process (cipher engines) consumes a lot of energy. Therefore, the memory data encryption method greatly increases the DRAM data transmission energy. In this paper, we propose a method to protect the data stored in DRAM itself from a cold boot attack without using data encryption, and thus, which protects the DRAM without consuming large interface energy. The Amnesiac DRAM proposed in this paper is a DRAM architecture which embeds a security function to prevent a cold boot attack. Amnesiac DRAM provides a countermeasure based on the observation that Cold Boot Attack requires the process of discharging the power in the DRAM module (at the time of module detachment) and re-supplying it (when connecting to another computer). Specifically, the Amnesiac DRAM blocks external access to the DRAM when power is supplied and erases all data stored in the DRAM. Amnesiac DRAM does not leak information stored in DRAM to the attacker because it allows user access after deleting all the data. Amnesiac DRAM is much more economical than the prior approaches because it has no penalty beyond the data initialization time and can easily be implemented in existing DRAMs.