(A) design of write driver for improved performance of multi-level cell phase change memory

Abstract

A demand for flash memory is expected to increase drastically, propelled by sales of smart devices such as smart phone and smart tablet. Although flash memory has been widely used as the storage device so far, the memory chip manufacturers are preparing the next generation non-volatile memory which has a better performance such as higher capacity, higher bandwidth and lower power consumption. In the emerging area of non volatile memory, phase change memory (PCM) is the most promising candidate to replace flash memory. In this thesis, overdrive write techniques are introduced to improve the performance of PCM write operation.

In chapter 1, the characteristics of the PCM cell material, GeSbTe (GST) and the conventional PCM cell structure using the GST are introduced. A basic operational principle for the cell programming is also presented.

In chapter 2, a write driver with an auto-scaling overdrive method is presented. The proposed overdrive method significantly reduces the rise time of the cell-current pulse for bit-line parasitic components of 3 pF and 6 kΩ, and it lowers the complexity of the overdrive control using an adaptive charge amplification technique. A rise time of less than 15 ns is achieved and shortened up to 4.7 times, and the total write-throughput is increased. The rise time is reduced consistently for all levels of the target-current by the auto-scaling effect. Therefore, cell heating control becomes more linear in program-and-verify (PNV) operation. Due to its simple adding-on structure, it is easily compatible with a conventional write driver. A prototype chip was implemented using a 0.18-$\mu$m CMOS process. It is also applicable to smaller-scale technology. In chapter 3, a write driver with a bit-line delay calibration for phase change memory applications is presented. A spike-shaping based overdrive technique greatly reduces the cell current settling time as well as minimizes its variation for variable cell locations. Thus, the transferred heating power for variable cell points becomes almost equivalent and the target cell resistance can quickly changes to the desired value even under high cell density condition. The proposed current driving scheme reduces the cell current settling time by 30 ns and minimizes the settling time variation by 83% for variable cell location. This chip was fabricated in 0.11 $\mu$m CMOS.