Design for capacitor-less low-dropout regulator with multi feedback loops and DC-DC converter using minimum power-loss tracking technique

Abstract

In Chapter 1, a novel capacitor-less low-dropout regulator (LDO) for mobile applications is presented. The proposed capacitor-less LDO utilizes multi feedback loops to satisfy several design challenges of capacitor-less LDO for mobile applications, at the same time, which are not considered in previous capacitor-less LDOs. To do so, the proposed LDO has a wide bandwidth of 3.03 MHz at load current of 150 mA with bias current of 40 $\mu$A, and the best line and load regulations of 0.0024 % / V and 0.0000417 % / mA, respectively, compared to previously reported LDOs. This chip has 100 mV dropout voltage and 150 mA maximum load current when using the power PMOS transistor of a 76,800 $\mu$m / 0.5 $\mu$m. Total capacitance of 29 pF was used the chip size of 0.279 $mm^2$.

In Chapter 2, DC-DC converter which guarantees minimum power loss under any condition is presented. In this DC-DC converter, a new approach for increasing power efficiency of DC-DC converter which imple-ments theoretical equations of minimum power loss intactly at the circuit level is adopted. In addition, since this approach has high reliability against process variations, DC-DC converter can achieve high power effi-ciency when IC is implemented in silicon level. This chip achieves power efficiency of around 90 % under various input and output voltage conditions.