Nanoscale patterning method and integrated device for electronic apparatus manufactured therefrom나노 스케일 패터닝 방법 및 이로부터 제조된 전자기기용 집적소자

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Provided is a nanoscale patterning method using self-assembly, wherein nanoscale patterns having desirable shapes such as a lamella shape, a cylinder shape, and the like, may be formed by using a self-assembly property of a block copolymer, and low segment interaction caused in a structure of 10 nm or less which is a disadvantage of the block copolymer may be prevented. In addition, even though single photolithography is used, pattern density may double as that of the existing nano patterns, and pitch and cycle of the patterns may be controlled to thereby be largely utilized for electronic apparatuses requiring high integration of circuits such as a semiconductor device, and the like.
Assignee
KAIST
Country
US (United States)
Issue Date
2017-11-07
Application Date
2014-12-26
Application Number
14583492
Registration Date
2017-11-07
Registration Number
9,812,333
URI
http://hdl.handle.net/10203/256922
Appears in Collection
MS-Patent(특허)
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