DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.contributor.author | Park, Jun-Young | ko |
dc.date.accessioned | 2019-04-15T15:57:05Z | - |
dc.date.available | 2019-04-15T15:57:05Z | - |
dc.date.issued | 2018-06-12 | - |
dc.identifier.uri | http://hdl.handle.net/10203/255477 | - |
dc.description.abstract | A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration). | - |
dc.title | Tunneling field-effect transistor with a plurality of nano-wires and fabrication method thereof | - |
dc.title.alternative | 복수의 나노와이어를 가진 터널링 전계효과 트랜지스터 및 그의 제조 방법 | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Park, Jun-Young | - |
dc.contributor.assignee | KAIST | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 15041559 | - |
dc.identifier.patentRegistrationNumber | 9,997,596 | - |
dc.date.application | 2016-02-11 | - |
dc.date.registration | 2018-06-12 | - |
dc.publisher.country | US | - |
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