Design and optimization of mesh clock network with multi-level clock gating
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 정진욱 | ko |
| dc.contributor.author | 이동수 | ko |
| dc.contributor.author | 신영수 | ko |
| dc.date.accessioned | 2019-04-15T15:55:10Z | - |
| dc.date.available | 2019-04-15T15:55:10Z | - |
| dc.date.created | 2014-11-26 | - |
| dc.date.issued | 2014-02-25 | - |
| dc.identifier.citation | 한국반도체학술대회 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/255443 | - |
| dc.language | Korean | - |
| dc.publisher | 대한전자공학회 | - |
| dc.title | Design and optimization of mesh clock network with multi-level clock gating | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | 한국반도체학술대회 | - |
| dc.identifier.conferencecountry | KO | - |
| dc.identifier.conferencelocation | 한양대학교 | - |
| dc.contributor.localauthor | 신영수 | - |
| dc.contributor.nonIdAuthor | 이동수 | - |
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