DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hong, Sung-Wan | ko |
dc.contributor.author | Kong, Tae-Hwang | ko |
dc.contributor.author | Park, Sang-Hui | ko |
dc.contributor.author | Park, Changbyung | ko |
dc.contributor.author | Jung, Seungchul | ko |
dc.contributor.author | Lee, Sungwoo | ko |
dc.contributor.author | Cho, Gyu-Hyeong | ko |
dc.date.accessioned | 2019-04-15T14:51:42Z | - |
dc.date.available | 2019-04-15T14:51:42Z | - |
dc.date.created | 2013-11-04 | - |
dc.date.issued | 2013-10 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, no.10, pp.2457 - 2468 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/254458 | - |
dc.description.abstract | This paper presents a novel on-chip compensation scheme, the Time-Mode Miller Compensation (TMMC), for DC-DC converter in which the compensation components are integrated on-chip. Using this proposed scheme, the DC-DC converter is stably compensated and insensitive to process variations, with significantly small compensation components (1 pF and 80 k Omega in this work) consuming very small silicon area owing to the characteristic of the TMMC. The small compensation components make the chip size small, with 0.12 mm(2) of core area (w/o power transistors) using 0.18 mu m I/O process. This core size is as small as that of the digital DC-DC converters implemented with less than sub-50 nm process. The measurement result shows that the maximum power efficiency of 90.6% is obtained at the load current of 220 mA with the switching frequency of 1.15 MHz when the input and the output voltages are 3.3 V and 2 V, respectively. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CIRCUITS | - |
dc.title | High Area-Efficient DC-DC Converter With High Reliability Using Time-Mode Miller Compensation (TMMC) | - |
dc.type | Article | - |
dc.identifier.wosid | 000324929700017 | - |
dc.identifier.scopusid | 2-s2.0-84884704903 | - |
dc.type.rims | ART | - |
dc.citation.volume | 48 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 2457 | - |
dc.citation.endingpage | 2468 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2013.2272845 | - |
dc.contributor.localauthor | Cho, Gyu-Hyeong | - |
dc.contributor.nonIdAuthor | Hong, Sung-Wan | - |
dc.contributor.nonIdAuthor | Kong, Tae-Hwang | - |
dc.contributor.nonIdAuthor | Park, Sang-Hui | - |
dc.contributor.nonIdAuthor | Park, Changbyung | - |
dc.contributor.nonIdAuthor | Jung, Seungchul | - |
dc.contributor.nonIdAuthor | Lee, Sungwoo | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Cost efficiency | - |
dc.subject.keywordAuthor | DC-DC power conversion | - |
dc.subject.keywordAuthor | Miller compensation | - |
dc.subject.keywordAuthor | on-chip compensation | - |
dc.subject.keywordAuthor | process variation | - |
dc.subject.keywordPlus | CIRCUITS | - |
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