High Area-Efficient DC-DC Converter With High Reliability Using Time-Mode Miller Compensation (TMMC)

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dc.contributor.authorHong, Sung-Wanko
dc.contributor.authorKong, Tae-Hwangko
dc.contributor.authorPark, Sang-Huiko
dc.contributor.authorPark, Changbyungko
dc.contributor.authorJung, Seungchulko
dc.contributor.authorLee, Sungwooko
dc.contributor.authorCho, Gyu-Hyeongko
dc.date.accessioned2019-04-15T14:51:42Z-
dc.date.available2019-04-15T14:51:42Z-
dc.date.created2013-11-04-
dc.date.issued2013-10-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, no.10, pp.2457 - 2468-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/254458-
dc.description.abstractThis paper presents a novel on-chip compensation scheme, the Time-Mode Miller Compensation (TMMC), for DC-DC converter in which the compensation components are integrated on-chip. Using this proposed scheme, the DC-DC converter is stably compensated and insensitive to process variations, with significantly small compensation components (1 pF and 80 k Omega in this work) consuming very small silicon area owing to the characteristic of the TMMC. The small compensation components make the chip size small, with 0.12 mm(2) of core area (w/o power transistors) using 0.18 mu m I/O process. This core size is as small as that of the digital DC-DC converters implemented with less than sub-50 nm process. The measurement result shows that the maximum power efficiency of 90.6% is obtained at the load current of 220 mA with the switching frequency of 1.15 MHz when the input and the output voltages are 3.3 V and 2 V, respectively.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectCIRCUITS-
dc.titleHigh Area-Efficient DC-DC Converter With High Reliability Using Time-Mode Miller Compensation (TMMC)-
dc.typeArticle-
dc.identifier.wosid000324929700017-
dc.identifier.scopusid2-s2.0-84884704903-
dc.type.rimsART-
dc.citation.volume48-
dc.citation.issue10-
dc.citation.beginningpage2457-
dc.citation.endingpage2468-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.identifier.doi10.1109/JSSC.2013.2272845-
dc.contributor.localauthorCho, Gyu-Hyeong-
dc.contributor.nonIdAuthorHong, Sung-Wan-
dc.contributor.nonIdAuthorKong, Tae-Hwang-
dc.contributor.nonIdAuthorPark, Sang-Hui-
dc.contributor.nonIdAuthorPark, Changbyung-
dc.contributor.nonIdAuthorJung, Seungchul-
dc.contributor.nonIdAuthorLee, Sungwoo-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorCost efficiency-
dc.subject.keywordAuthorDC-DC power conversion-
dc.subject.keywordAuthorMiller compensation-
dc.subject.keywordAuthoron-chip compensation-
dc.subject.keywordAuthorprocess variation-
dc.subject.keywordPlusCIRCUITS-
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