DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Kyung Min | ko |
dc.contributor.author | Xu, Nuo | ko |
dc.contributor.author | Shao, Xinglong | ko |
dc.contributor.author | Yoon, Kyung Jean | ko |
dc.contributor.author | Kim, Hae Jin | ko |
dc.contributor.author | Williams, R. Stanley | ko |
dc.contributor.author | Hwang, Cheol Seong | ko |
dc.date.accessioned | 2019-04-15T14:15:52Z | - |
dc.date.available | 2019-04-15T14:15:52Z | - |
dc.date.created | 2019-03-26 | - |
dc.date.issued | 2019-03 | - |
dc.identifier.citation | PHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS, v.13, no.3 | - |
dc.identifier.issn | 1862-6254 | - |
dc.identifier.uri | http://hdl.handle.net/10203/254002 | - |
dc.description.abstract | By combining the functions of Boolean gates and non-volatile memory, stateful logic may enable significant savings in time and energy for computational processes that can be performed directly in main memory and for data analyses in edge environments. A simple reduction to practice this concept is demonstrated by Borghetti et al. in 2010 via a material implication logic gate comprising two parallel memristors and a conditional write operation. Here, a single physical dual-bit memristor, possessing both bipolar and unipolar resistance switching characteristics and utilizing their operations, is demonstrated. This device responds to a conditional write to perform not only implication but multiple other logic functions when configured with a series resistor and addressed with a specific voltage pulse. The simple circuit structure of this dual-bit memristor allows compact sequential logic cascading along the time dimension without a concern of multiple cell accessing related issues. The sequence of implementing a full-adder is also discussed. | - |
dc.language | English | - |
dc.publisher | WILEY-V C H VERLAG GMBH | - |
dc.title | Single-Cell Stateful Logic Using a Dual-Bit Memristor | - |
dc.type | Article | - |
dc.identifier.wosid | 000460697100001 | - |
dc.identifier.scopusid | 2-s2.0-85058977915 | - |
dc.type.rims | ART | - |
dc.citation.volume | 13 | - |
dc.citation.issue | 3 | - |
dc.citation.publicationname | PHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS | - |
dc.identifier.doi | 10.1002/pssr.201800629 | - |
dc.contributor.localauthor | Kim, Kyung Min | - |
dc.contributor.nonIdAuthor | Xu, Nuo | - |
dc.contributor.nonIdAuthor | Shao, Xinglong | - |
dc.contributor.nonIdAuthor | Yoon, Kyung Jean | - |
dc.contributor.nonIdAuthor | Kim, Hae Jin | - |
dc.contributor.nonIdAuthor | Williams, R. Stanley | - |
dc.contributor.nonIdAuthor | Hwang, Cheol Seong | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | in-memory computation | - |
dc.subject.keywordAuthor | logic in memory | - |
dc.subject.keywordAuthor | memristor | - |
dc.subject.keywordAuthor | multilevel storage | - |
dc.subject.keywordAuthor | stateful logic | - |
dc.subject.keywordPlus | OPERATIONS | - |
dc.subject.keywordPlus | MECHANISMS | - |
dc.subject.keywordPlus | MEMORIES | - |
dc.subject.keywordPlus | ARRAY | - |
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