Single-Cell Stateful Logic Using a Dual-Bit Memristor

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dc.contributor.authorKim, Kyung Minko
dc.contributor.authorXu, Nuoko
dc.contributor.authorShao, Xinglongko
dc.contributor.authorYoon, Kyung Jeanko
dc.contributor.authorKim, Hae Jinko
dc.contributor.authorWilliams, R. Stanleyko
dc.contributor.authorHwang, Cheol Seongko
dc.date.accessioned2019-04-15T14:15:52Z-
dc.date.available2019-04-15T14:15:52Z-
dc.date.created2019-03-26-
dc.date.issued2019-03-
dc.identifier.citationPHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS, v.13, no.3-
dc.identifier.issn1862-6254-
dc.identifier.urihttp://hdl.handle.net/10203/254002-
dc.description.abstractBy combining the functions of Boolean gates and non-volatile memory, stateful logic may enable significant savings in time and energy for computational processes that can be performed directly in main memory and for data analyses in edge environments. A simple reduction to practice this concept is demonstrated by Borghetti et al. in 2010 via a material implication logic gate comprising two parallel memristors and a conditional write operation. Here, a single physical dual-bit memristor, possessing both bipolar and unipolar resistance switching characteristics and utilizing their operations, is demonstrated. This device responds to a conditional write to perform not only implication but multiple other logic functions when configured with a series resistor and addressed with a specific voltage pulse. The simple circuit structure of this dual-bit memristor allows compact sequential logic cascading along the time dimension without a concern of multiple cell accessing related issues. The sequence of implementing a full-adder is also discussed.-
dc.languageEnglish-
dc.publisherWILEY-V C H VERLAG GMBH-
dc.titleSingle-Cell Stateful Logic Using a Dual-Bit Memristor-
dc.typeArticle-
dc.identifier.wosid000460697100001-
dc.identifier.scopusid2-s2.0-85058977915-
dc.type.rimsART-
dc.citation.volume13-
dc.citation.issue3-
dc.citation.publicationnamePHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS-
dc.identifier.doi10.1002/pssr.201800629-
dc.contributor.localauthorKim, Kyung Min-
dc.contributor.nonIdAuthorXu, Nuo-
dc.contributor.nonIdAuthorShao, Xinglong-
dc.contributor.nonIdAuthorYoon, Kyung Jean-
dc.contributor.nonIdAuthorKim, Hae Jin-
dc.contributor.nonIdAuthorWilliams, R. Stanley-
dc.contributor.nonIdAuthorHwang, Cheol Seong-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorin-memory computation-
dc.subject.keywordAuthorlogic in memory-
dc.subject.keywordAuthormemristor-
dc.subject.keywordAuthormultilevel storage-
dc.subject.keywordAuthorstateful logic-
dc.subject.keywordPlusOPERATIONS-
dc.subject.keywordPlusMECHANISMS-
dc.subject.keywordPlusMEMORIES-
dc.subject.keywordPlusARRAY-
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