DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Chang-Gyu | ko |
dc.contributor.author | Lee, Won-Jong | ko |
dc.date.accessioned | 2011-09-01T02:23:51Z | - |
dc.date.available | 2011-09-01T02:23:51Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2011-03 | - |
dc.identifier.citation | JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, v.29, no.2, pp.020604-1 - 020604-6 | - |
dc.identifier.issn | 1071-1023 | - |
dc.identifier.uri | http://hdl.handle.net/10203/25062 | - |
dc.description.abstract | As the aspect ratio of a via increases, the film sputter-deposited inside the via suffers from poor step coverage. In this study, the authors introduced a partially tapered via and simulated the thickness profile of sputter-deposited film inside it. For the simulation, the directionality factor k was introduced to the Monte Carlo method to consider the angular directionality of depositing atoms. The optimum partially tapered via, which has a maximum sidewall coverage, was obtained for various via dimensions (i.e., aspect ratios and bottom-to-entrance size ratios) and directionality factors of depositing atoms. The enhancement effect of the sidewall coverage by introducing an optimum partially tapered via was investigated quantitatively. The enhancement factor of an optimum partially tapered via is always greater than that of a fully tapered via. To achieve high sidewall coverage for high aspect ratio vias, it is suggested to deposit a film inside an optimum partially tapered via under the condition with high directionality. (C) 2011 American Vacuum Society. [DOI: 10.1116/1.3567184] | - |
dc.description.sponsorship | This work was supported by the new growth engine semiconductor project of the Ministry of Knowledge and Economy Grant No. 10029009. | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | A V S Amer Inst Physics | - |
dc.subject | THROUGH-SILICON VIAS | - |
dc.subject | 3-DIMENSIONAL INTEGRATION | - |
dc.subject | STEP COVERAGE | - |
dc.subject | TOPOGRAPHY | - |
dc.subject | SIMULATION | - |
dc.subject | FABRICATION | - |
dc.title | Quantitative study on the enhancement of sidewall coverage of sputter-deposited film by partially tapering the sidewall of via holes | - |
dc.type | Article | - |
dc.identifier.wosid | 000289166000004 | - |
dc.identifier.scopusid | 2-s2.0-79953785405 | - |
dc.type.rims | ART | - |
dc.citation.volume | 29 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 020604-1 | - |
dc.citation.endingpage | 020604-6 | - |
dc.citation.publicationname | JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Lee, Won-Jong | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordPlus | THROUGH-SILICON VIAS | - |
dc.subject.keywordPlus | 3-DIMENSIONAL INTEGRATION | - |
dc.subject.keywordPlus | STEP COVERAGE | - |
dc.subject.keywordPlus | TOPOGRAPHY | - |
dc.subject.keywordPlus | SIMULATION | - |
dc.subject.keywordPlus | FABRICATION | - |
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