DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Sang-Hyeon | ko |
dc.contributor.author | Kim, Seong-Kwang | ko |
dc.contributor.author | Shim, Jae-Phil | ko |
dc.contributor.author | Geum, Dae-Myeong | ko |
dc.contributor.author | Ju, Gunwu | ko |
dc.contributor.author | Kim, Han-Sung | ko |
dc.contributor.author | Lim, Hee-Jeong | ko |
dc.contributor.author | Lim, Hyeong-Rak | ko |
dc.contributor.author | Han, Jae-Hoon | ko |
dc.contributor.author | Lee, Subin | ko |
dc.contributor.author | Kim, Ho-Sung | ko |
dc.contributor.author | Bidenko, Pavlo | ko |
dc.contributor.author | Kang, Chang-Mo | ko |
dc.contributor.author | Lee, Dong-Seon | ko |
dc.contributor.author | Song, Jin-Dong | ko |
dc.contributor.author | Choi, Won Jun | ko |
dc.contributor.author | Kim, Hyung-Jun | ko |
dc.date.accessioned | 2019-02-20T04:57:41Z | - |
dc.date.available | 2019-02-20T04:57:41Z | - |
dc.date.created | 2019-02-07 | - |
dc.date.issued | 2018 | - |
dc.identifier.citation | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v.6, no.1, pp.579 - 587 | - |
dc.identifier.issn | 2168-6734 | - |
dc.identifier.uri | http://hdl.handle.net/10203/250256 | - |
dc.description.abstract | Monolithic 3-D integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order to ensure proper performance of bottom side devices. To solve this problem, we developed a low temperature III-V and Ge layer stacking process using wafer bonding and epitaxial lift-off, since these materials can be processed at a low temperature and provide extended opportunity/functionality (sensor, display, analog, RF, etc.) via heterogeneous integration. In this paper, we discuss technology for integrating III-V and Ge materials and its applicability to CMOS, thin film photodiodes, mid-infrared photonics platforms, and MicroLED display integration for creating the ultimate 3-D chip of the future. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III-V and Ge Materials | - |
dc.type | Article | - |
dc.identifier.wosid | 000435505000006 | - |
dc.identifier.scopusid | 2-s2.0-85041506010 | - |
dc.type.rims | ART | - |
dc.citation.volume | 6 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 579 | - |
dc.citation.endingpage | 587 | - |
dc.citation.publicationname | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | - |
dc.identifier.doi | 10.1109/JEDS.2018.2802840 | - |
dc.contributor.nonIdAuthor | Kim, Seong-Kwang | - |
dc.contributor.nonIdAuthor | Shim, Jae-Phil | - |
dc.contributor.nonIdAuthor | Geum, Dae-Myeong | - |
dc.contributor.nonIdAuthor | Ju, Gunwu | - |
dc.contributor.nonIdAuthor | Kim, Han-Sung | - |
dc.contributor.nonIdAuthor | Lim, Hee-Jeong | - |
dc.contributor.nonIdAuthor | Lim, Hyeong-Rak | - |
dc.contributor.nonIdAuthor | Han, Jae-Hoon | - |
dc.contributor.nonIdAuthor | Lee, Subin | - |
dc.contributor.nonIdAuthor | Kim, Ho-Sung | - |
dc.contributor.nonIdAuthor | Bidenko, Pavlo | - |
dc.contributor.nonIdAuthor | Kang, Chang-Mo | - |
dc.contributor.nonIdAuthor | Lee, Dong-Seon | - |
dc.contributor.nonIdAuthor | Song, Jin-Dong | - |
dc.contributor.nonIdAuthor | Choi, Won Jun | - |
dc.contributor.nonIdAuthor | Kim, Hyung-Jun | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
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