Fast timing analysis of non-tree clock network with shorted wires

Abstract

A non-tree clock network, such as crosslink and mesh, includes some shorted wires to reduce clock skew. A short-circuit current that flows through the shorted wires makes conventional static timing analysis (STA) inapplicable. Transistor-level simulation may be applied but takes long time. We address a fast timing analysis of non-tree clock network. A partial circuit made of drivers, shorted wires, and receivers is extracted and represented as voltage-dependent current sources with p-model of RC load. Given voltage waveforms at driver inputs, we calculate the waveform at each shorted node by repeating nodal analysis for each time step; the waveform is represented as piecewise linear function. As the waveform propagates to receiver input via RC tree, the responses for all linear segments are obtained and merged into a full waveform. The waveform at receiver input then passes through receiver to produce a linear waveform at receiver output. Finally, timing parameters from the waveform at receiver output are transferred to STA, such that it utilizes the parameters to analyze the remaining circuit from receiver outputs to clock sinks. Experiments with a few test circuits demonstrate that analysis time is reduced by 10x with only 1% error on average ( both in delay and transition time) compared to SPICE.