Library Optimization for Near-Threshold Voltage Design

Abstract

A circuit operating at near-threshold voltage (NTV) dissipates much less energy, but it suffers from significant increase in cell delay as well as delay variation. In this paper, we address two library optimization methods for NTV design: (1) transistor lengths are increased to benefit from reverse short channel effect (RSCE), and (2) each flip-flop is optimized into a few versions with different timing parameters by redistributing clock signals to clocked transistors. Flip-flops are remapped to optimized ones via integer linear programming (ILP); a goal is to minimize total negative slack (TNS) under hold time constraints, which is a critical concern in NTV design. Experiments demonstrate that our proposed method achieves 22%, 56%, and 13% reductions in clock period, energy dissipation, and circuit area, respectively, on average of a few test circuits in 55-nm technology.