Memory-efficient hardware implementation of guided image filter

Abstract

Guided Image Filter (GIF) finds many applications such as image denoising, matting, dehazing, HDR compression, stereo matching, scene enhancement, and texture classification, for example, due to its edge preservation. For real-time applications an efficient hardware implementation of the GIF is indispensable. Based on analysis, previous implementations focused on reducing the logic complexity but reduction of memory requirement remained unaddressed. Here two memory efficient architectures for implementation of Guided Image Filter (GIF) in Field Programmable Gate Array (FPGA) are proposed. Since the GIF involves six box filters, its memory requirement is very high. To reduce memory requirement it is proposed in the first architecture to use intermediate coefficients (a and b in the algorithm) without taking mean to generate the output when input and guide images are the same. As bit widths of these coefficients are very high, the memory requirement is reduced by 83.33% while maintaining the quality of output image. In this design 31.57% frequency gain is obtained with equal power consumption compared to the state-of-the-art implementation. In the second design,a parallel architecture is proposed to calculate the mean of the intermediate coefficients when input and guide images are different. In this way, the proposed architecture reduces memory requirement by 66.67% with an affordable increase in power and combinational logic. A new two region add and shift-based method to approximate log2 in hardware is proposed to replace complex division operation. The proposed approach results in 81.55% less percentage error and 42.85% less average error compared to previously reported best two region based approximation approaches with comparable area cost and latency . Both proposed designs for the GIF are implemented on Virtex-7 and thoroughly verified.