RF low noise downconverter front-end design for 2.4 GHz Ultra Low Power Transceivers

Abstract

An ultra-low power (ULP) Front-end consisting a high gain low noise amplifier (LNA) and a high linearity mixer in a standard 65nm CMOS is presented. The forward body biased, complementary input stage provides transconductance boosting and a robust on-chip input match under two operational modes. Chip area efficiency is increased by the self-biased inverter stage requiring only two inductors for input matching and inter-stage isolation, compared to three inductors needed in conventional LNA. The current reused, stacked, NMOS-common-source output stage provides additional gain with no added DC power, and reutilizes the inter-stage isolation inductor to form the output impedance peaking LC tank. A Gain reduction method is added to the output stage to enhance the LNA dynamic range. For RF down-conversion, a single balanced passive mixer adopting a complementary type switch with both LO-IF and LO-RF rejection is cascaded to the LNA output. The Front-end operates as a high linearity voltage down converter. Fabricated with fully on-chip components, Front-end achieves 23 dB conversion gain, 8 dB NF, -36 dBm P1dB and -21 dBm IIP3 while dissipating 64 uW power from a 0.6 V supply. The LNA achieves a voltage gain of 26 dB and minimum NF of 5.5 dB. In gain lowered mode, LNA achieves P1dB of -27 dBm and IIP3 of -13 dBm, while dissipating a maximum power of 69 uW from a 0.6 V supply. Full front achieves 23 dB conversion gain, 8 dB NF and -21 dBm IIP3, and is well suited for ULP IoT RF front-end receivers.