Automatic clock gating synthesis of gate-level netlist = 게이트 레벨 넷리스트의 클럭 게이팅 자동 합성

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Clock gating has now become a standard design practice, and it is generally applied during RTL design stage. RTL clock gating has two significant limitations: the designer has to provide a gating funtion; and registers whose gating functions are not specified are left ungated. Gate-level clock gating, which is proposed to resolve these problems, automatically inserts clock gating structures into a given netlist. It consists of three steps: extracting a gating condition for each flip-flop; register grouping which classifies flip-flops into multiple groups so that the flip-flops in a same group are gated together; and adding ICG cells and the gates required to implement a gating condition for each flip-flop group. We propose a method of extracting gating conditions through detection of cyclic paths which increases the number of gated flip-flops by reducing the overhead of gating logic. We also suggest balanced register grouping to reduce the number of ICG cells and fast estimation of gating logic power. Implementation of gating conditions with least amount of additional gates is also discussed.
Advisors
Shin, Young Sooresearcher신영수researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2017
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2017.8,[vi, 67 p. :]

Keywords

clock gating▼aregister grouping▼agating logic▼acyclic path▼amaximum weight matching▼alogic simplification; 클럭 게이팅▼a레지스터 그룹핑▼a게이팅 로직▼a순환 경로▼a최대 가중치 매칭▼a로직 간소화

URI
http://hdl.handle.net/10203/242061
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=718945&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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