학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2017.8,[vi, 67 p. :]
clock gating▼aregister grouping▼agating logic▼acyclic path▼amaximum weight matching▼alogic simplification; 클럭 게이팅▼a레지스터 그룹핑▼a게이팅 로직▼a순환 경로▼a최대 가중치 매칭▼a로직 간소화
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.