(A) power-and-area efficient bootstrap transceiver for referenceless and lane-independent operation

Abstract

Parallel transceivers are being adopted to increase the data throughput in high-speed serial link applications. A phase interpolator (PI)-based clock and data recovery (CDR) architecture is better suited for parallel transceiver applications than its voltage-controlled oscillator (VCO)-based counterparts, because of its power and area efficiency and its robustness to interference. A PI-based bootstrap transceiver for referenceless and lane-independent operation is presented. PI output clock signals phase locked to the input data are used as reference clock signals for frequency locking the VCO. The VCO clock signal is then redistributed to the PIs, triggering the bootstrapping between the VCO and the PIs. All lanes operate independently as in VCO-based parallel referenceless designs while saving power and area.