DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Tag Gon Kim | - |
dc.contributor.advisor | 김탁곤 | - |
dc.contributor.author | Seok, Moon-Gi | - |
dc.contributor.author | 석문기 | - |
dc.date.accessioned | 2018-05-23T19:37:20Z | - |
dc.date.available | 2018-05-23T19:37:20Z | - |
dc.date.issued | 2017 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=675810&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/242012 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2017.2,[v, 66 p. :] | - |
dc.description.abstract | It is becoming essential to design a mixed-signal system-on-chip (SoC) based on the intellectual property (IP) due to the rapid time-to-market (TAT) requirement. The IPs have been implemented using various hardware description languages (HDLs) depending on target abstraction levels and signal types with the corresponding resolution. This heterogeneity leads to challenges in simulation to evaluate simultaneously assembled IPs of the prototypes. One traditional solution is to convert related heterogeneous IP models into equivalent models, that are described in a single description language. This conversion approach often requires manual rewriting of existing IPs, and this results in description loss during the model projection due to the absence of corresponding modeling syntaxes. The other solutions are co-simulation/emulation approaches that are based on the coupling of multiple simulators/emulators through connection modules. The conventional methods do not have formal theoretical backgrounds and an explicit interface for integrating the simulator into their solutions. In this dissertation, we propose a formal and distributed co-simulation approach based on the high-level architecture (HLA) and a newly-defined programming language interface for interoperation (PLI-I) between heterogeneous IPs as a formal simulator interface. Based on the proposed PLI-I and HLA, we introduce formal procedures of integration and interoperation. To reduce integration costs, we split these procedures into two parts: a reusable common library and an additional model-dependent signal-to-event (SE) converter to handle differently abstracted in/out signals between the coupled IPs. During the interoperation, to resolve the different time-advance mechanisms and increase computation concurrency between digital and analog simulators, the proposed co-simulation approach performs an advanced HLA-based synchronization using the pre-simulation concepts. The case study shows the validation of interoperation behaviors between the heterogeneous IPs in mixed-signal SoC design, the reduced design effort in integrating, and the synchronization speedup using the proposed approach. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | HLA/RTI | - |
dc.subject | co-simulation | - |
dc.subject | mixed-signal system-on-chip | - |
dc.subject | interoperation | - |
dc.subject | pre-simulation | - |
dc.subject | 코시뮬레이션 | - |
dc.subject | 혼합신호 시스템 온 칩 | - |
dc.subject | 연동 | - |
dc.subject | 선시뮬레이션 | - |
dc.title | HLA-based Co-simulation in mixed-signal system-on-chip design | - |
dc.title.alternative | 혼합 신호 시스템 온칩 설계를 위한 HLA 기반의 코시뮬레이션 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
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