DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Seong Joong | ko |
dc.date.accessioned | 2018-03-23T00:13:57Z | - |
dc.date.available | 2018-03-23T00:13:57Z | - |
dc.date.created | 2018-03-20 | - |
dc.date.created | 2018-03-20 | - |
dc.date.issued | 2018-03 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.54, no.5, pp.327 - 328 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/240916 | - |
dc.description.abstract | A robust 400 MHz super-regenerative receiver with low susceptibility to clock jitter is proposed. The conventional un-clocked envelope detector (ED) is replaced with a synchronous peak-held ED, where its peak detection value is kept during oscillator quenching OFF time by switching off the charging path of ED, synchronously with quenching clock. In this way, the flattened peak level not only allows the use of low quality jitter in the clock but also removes a tedious timing calibration process in the conventional receiver. The proposed receiver with the novel synchronous peak-held ED and an on-chip oscillator achieves a sensitivity performance of -81 dBm@1 Mbps without the conventional ADC sampling timing calibration. The receiver in 180 nm CMOS occupies an active area of 0.51 mm(2) and dissipates 570 mu W. | - |
dc.language | English | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.title | Robust super-regenerative receiver with low susceptibility on clock jitter employing synchronous peak-held envelope detector | - |
dc.type | Article | - |
dc.identifier.wosid | 000426262200039 | - |
dc.identifier.scopusid | 2-s2.0-85042803481 | - |
dc.type.rims | ART | - |
dc.citation.volume | 54 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 327 | - |
dc.citation.endingpage | 328 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.identifier.doi | 10.1049/el.2017.4536 | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | CMOS analogue integrated circuits | - |
dc.subject.keywordAuthor | radio receivers | - |
dc.subject.keywordAuthor | robust super-regenerative receiver | - |
dc.subject.keywordAuthor | clock jitter | - |
dc.subject.keywordAuthor | synchronous peak-held envelope detector | - |
dc.subject.keywordAuthor | un-clocked envelope detector | - |
dc.subject.keywordAuthor | synchronous peak-held ED | - |
dc.subject.keywordAuthor | peak detection value | - |
dc.subject.keywordAuthor | oscillator quenching OFF time | - |
dc.subject.keywordAuthor | flattened peak level | - |
dc.subject.keywordAuthor | low-quality jitter | - |
dc.subject.keywordAuthor | timing calibration process | - |
dc.subject.keywordAuthor | on-chip oscillator | - |
dc.subject.keywordAuthor | sensitivity performance | - |
dc.subject.keywordAuthor | frequency 400 MHz | - |
dc.subject.keywordAuthor | size 180 nm | - |
dc.subject.keywordAuthor | power 570 muW | - |
dc.subject.keywordAuthor | bit rate 1 Mbit | - |
dc.subject.keywordAuthor | s | - |
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