DC Field | Value | Language |
---|---|---|
dc.contributor.author | 신영수 | ko |
dc.date.accessioned | 2017-12-20T12:56:13Z | - |
dc.date.available | 2017-12-20T12:56:13Z | - |
dc.date.issued | 2010-07-13 | - |
dc.identifier.uri | http://hdl.handle.net/10203/236587 | - |
dc.description.abstract | A low power semiconductor memory device using a power gating is disclosed. The semiconductor memory device includes a standard cell and a power gating cell. The standard cell is provided with a virtual supply voltage and a first supply voltage. The power gating cell generates the virtual supply voltage from a second supply voltage and provides the standard cell with the virtual supply voltage in response to a control signal. The virtual supply voltage and the first supply voltage are provided by a first metal layer and the second supply voltage is provided by a third metal layer. The power gating cell may include at least one slice block and isolator blocks. The respective slice block has a transistor for switching current. The isolator blocks are arranged on both sides of the slice block and insulate the slice block from outside. | - |
dc.title | Power network using standard cell, power gating cell, and semiconductor device using the power network | - |
dc.title.alternative | 표준 셀과 파워 게이팅 셀을 이용한 파워 네트워크 및 이를 가지는 반도체 장치 | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | 신영수 | - |
dc.contributor.assignee | KAIST | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 11741995 | - |
dc.identifier.patentRegistrationNumber | 7755396 | - |
dc.date.application | 2007-04-30 | - |
dc.date.registration | 2010-07-13 | - |
dc.publisher.country | US | - |
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