DC Field | Value | Language |
---|---|---|
dc.contributor.author | 조규형 | ko |
dc.date.accessioned | 2017-12-20T12:48:15Z | - |
dc.date.available | 2017-12-20T12:48:15Z | - |
dc.date.issued | 2004-04-27 | - |
dc.identifier.uri | http://hdl.handle.net/10203/236494 | - |
dc.description.abstract | Disclosed are flat panel field emitter displays whose unit cell structure adopt a planar cathode structure in stead of a conventional microtip structure, so as to increase the degree of integration and can be operated at low operation voltages at high speeds. In the structure, a channel insulator is formed below the cathode and underlaid by a gate. By means of the gate voltage, the electron emission from the cathode can be controlled. The electrodes in the structure are arranged in the order of anode, cathode and gate, allowing the simplification of processes. With the ease of controlling the distance between electrodes, the displays can be applied for almost all video systems from small sizes to large screen area displays, in place of conventional displays. The displays allows conventional semiconductor processes and facilities to be utilized as they are. | - |
dc.title | Flat field emitter displays | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | 조규형 | - |
dc.contributor.assignee | KAIST | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 09646730 | - |
dc.identifier.patentRegistrationNumber | 6727642 | - |
dc.date.application | 2000-09-20 | - |
dc.date.registration | 2004-04-27 | - |
dc.publisher.country | US | - |
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