Browse "RIMS Collection" by Subject delay-locked loop
Showing results 1 to 3 of 3
| A 500-Mb/a quadruple data rate SDRAM interface using a skew cancellation technique Wang, SH; Kim, J; Lee, J; Nam, HS; Kim, YG; Shim, JH; Ahn, HK; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.4, pp.648 - 657, 2001-04 |
| A DLL-based frequency synthesizer with selective reuse of a delay cell scheme for 2.4 GHz ISM band Kang, S; Kim, Beom-Sup, IEICE TRANSACTIONS ON ELECTRONICS, v.E88C, no.1, pp.149 - 153, 2005 |
| A Low-Jitter Mixed-Mode DLL for Hign-Speed DRAM Applications j. j. kim; s.-b. lee; t. -s. jung; c.-h. kim; s.-i. cho; b. kim, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.35, no.10, pp.1430 - 1436, 2000-10 |
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