Browse "RIMS Collection" by Author Sharma, Hardik
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| Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks Sharma, Hardik; PARK, JONGSE; Suda, Naveen; Lai, Liangzhen; Chau, Benson; Chandra, Vikas; Esmaeilzadeh, Hadi, International Symposium on Computer Architecture (ISCA), ACM/IEEE, 2018-06-03 |
| From High-Level Deep Neural Models to FPGAs Sharma, Hardik; PARK, JONGSE; Mahajan, Divya; Amaro, Emmanuel; Kim, Joon Kyung; Shao, Chenkai; Mishra, Asit; et al, International Symposium on Microarchitecture (MICRO), IEEE and ACM SIGMICRO, 2016-10-15 |
| Scale-Out Acceleration for Machine Learning PARK, JONGSE; Sharma, Hardik; Mahajan, Divya; Kim, Joon Kyung; Olds, Preston; Esmaeilzadeh, Hadi, International Symposium on Microarchitecture (MICRO), IEEE and ACM SIGMICRO, 2017-10-14 |
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