Browse "RIMS Collection" by Author Seung-Ho Hwang

Showing results 1 to 13 of 13

1
Abstract Simulator : A Sotfware Timing analysis Tool

Seung-Ho Hwang, International Conference on Signal Processing Applications and Technology, pp.890 - 894, 1996

2
An Accurate Delay Modeling Technique for Switch - level Timing Verification

Seung-Ho Hwang, ACM/IEEE Design Automation Conference, pp.227 - 233, 1986

3
An Automated Electron-Beam Diagnostic System

Seung-Ho Hwang, Japanese Electron-Beam Testing Symposium, 1990

4
An Educational and Learning kit for VHDL Modeling and ASIC Implementation

Seung-Ho Hwang, The Electronic Design Autimation & Test Conference and Exhibition, 1994

5
An Efficient Design Correctness Checker of Finite-State Machines

Seung-Ho Hwang, Proceedings of IEEE International Conference on Computer-Aided Design, pp.410 - 413, 1987

6
An Erolution Algorithm for Microcock Bit Optimiqation

Seung-Ho Hwang, The first Asia-Pacific Conference on Simulated Erolution and Learnirg, pp.217 - 223, 1996

7
BEAVER: A Behavioral Formal Verifier of VLSI Design

Seung-Ho Hwang, IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, 1989

8
Design of a DCT/IDCT Processor

Seung-Ho Hwang, 대한전자공학회 '95 DSP Workshop, 1995

9
Design of Wave-Pipelined 900MHz 16b Ripple-Carry Adder Using Modified NPCPL

Seung-Ho Hwang, IEEE International Symposium on Circuits and Systems, pp.207 - 209, 1996

10
Proportional-Integral Plus Bang-Bang Control of DC Servo Motors with PWM Drives

Bien, Zeung nam; Seung-Ho Hwang, World Congress International Federation of Automatic Control, pp.282 - 286, 1984

11
Tackling EMI in Flat-Panel Displays

Seung-Ho Hwang, International Microelectronics and Packaging Society, Advanced Technology Workshop: Flat Panel Displays, 1996

12
Techniques for Special Instruction Generation for DSP ASIP

Seung-Ho Hwang, 5th Asia Pacific Conference on Hardware Description Languages(APCHDL'98), 1998

13
Technology Mapping for Storage Elements Based on BDD Matching

Seung-Ho Hwang, IEEE International Workshop on Logic Synthesis, 1997

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