Showing results 32 to 43 of 43
Low Jitter Digital Timing Synchronizer for CAP-based VDSL System Beom-Sup Kim, European Solid-State Circuits Conference, pp.146 - 147, 2001 |
Low Noise Clock Synthesizer Design Using Optimal Bandwidth Beom-Sup Kim, IEEE International Symposium on Circuits and Systems, 1998 |
Low power Circuit Design Issues 김범섭, 저전압, 저전력 VLSI Workshop, 1995 |
Low Power CMOS on Chip Voltage Reference Using MOS PTAT Beom-Sup Kim, IEEE International ASIC conference, pp.316 - 320, 1997 |
MIGHTI : A High Performance 16-bit DSP for Mobile Communication Applications Beom-Sup Kim, European Solid-State Circuits Conference (ESSCIRC '98), 1998 |
MIxed-Mode Synchronization in Digital Communication 김범섭, CAD 및 VLSI, 1996 |
Optimal MMSE Gear-Shifting Algorithm for the Fast Synchronization of DPLL Beom-Sup Kim, IEEE International Symposium on Circuit and Systems, pp.172 - 175, 1993 |
PLL/DLL system noise analysis for low jitter clock synthesizer design Kim Beomsup; Weigandt Todd C.; Gray Paul R., Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), v.4, pp.31 - 34, 1994-05-30 |
Skew에 둔감한 광대역 입출력용 Delay Locked Loop 김범섭, CAD 및 VLSI, 1998 |
The Research on the Effective Algorithm for Device Simulation 김범섭, KIEE Semiconductor and CAD Research Conference, pp.19 - 22, 1985 |
저전력 칩상 전압 안정기 설계 김범섭, 대한전자공학회 학술발표회, 1996 |
칩상 튜닝회로를 포함한 3.0V 연속시간 저대역 필터의 설계 김범섭, CAD 및 VLSI, 1996 |
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