METHOD FOR MANUFACTURING HETERO JUNCTION BIPOLAR TRANSISTOR
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 홍성철 | ko |
| dc.date.accessioned | 2017-12-20T11:13:42Z | - |
| dc.date.available | 2017-12-20T11:13:42Z | - |
| dc.date.issued | 2002-10-01 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/233633 | - |
| dc.description.abstract | Disclosed is a method for manufacturing a hetero junction bipolar transistor capable of forming a ledge by using a low-priced contact aligner and in a selective wet etching manner, without having any expensive stepper and dry etching and forming a ballasting resistor, without having an additional NiCr thin film, whereby the manufacturing processes thereof can be embodied in simple and easy manners, thereby improving productivity and an economical efficiency. | - |
| dc.title | METHOD FOR MANUFACTURING HETERO JUNCTION BIPOLAR TRANSISTOR | - |
| dc.type | Patent | - |
| dc.type.rims | PAT | - |
| dc.contributor.localauthor | 홍성철 | - |
| dc.contributor.assignee | KAIST | - |
| dc.identifier.iprsType | 특허 | - |
| dc.identifier.patentApplicationNumber | PCT/KR2000/000974 | - |
| dc.identifier.patentRegistrationNumber | 6,458,668 | - |
| dc.date.application | 2000-08-29 | - |
| dc.date.registration | 2002-10-01 | - |
| dc.publisher.country | KO | - |
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