Method for manufacturing SrTiO3series varistor using grain boundary segregation입계편석을 이용한 SrTiO₃계 베리스터의 제조방법
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 강석중 | ko |
| dc.date.accessioned | 2017-12-20T10:29:00Z | - |
| dc.date.available | 2017-12-20T10:29:00Z | - |
| dc.date.issued | 2010-05-11 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/232542 | - |
| dc.description.abstract | The present invention relates to a method for manufacturing a SrTiO3 series varistor using grain boundary segregation, and more particularly, to a method for manufacturing a SrTiO3 series varistor by sintering a powdered composition in which acceptors such as Al and Fe are added in powdered form and then sintered under a reducing atmosphere and heat-treated them in the air to selectively form electrical conduction barriers at grain boundaries in a process for manufacturing SrTiO3 series varistor having an excellent non-linear coefficient and a breakdown voltage suitable for use. | - |
| dc.title | Method for manufacturing SrTiO3series varistor using grain boundary segregation | - |
| dc.title.alternative | 입계편석을 이용한 SrTiO₃계 베리스터의 제조방법 | - |
| dc.type | Patent | - |
| dc.type.rims | PAT | - |
| dc.contributor.localauthor | 강석중 | - |
| dc.contributor.assignee | KAIST | - |
| dc.identifier.iprsType | 특허 | - |
| dc.identifier.patentApplicationNumber | 11709291 | - |
| dc.identifier.patentRegistrationNumber | 7714695 | - |
| dc.date.application | 2007-02-22 | - |
| dc.date.registration | 2010-05-11 | - |
| dc.publisher.country | US | - |
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