Semiconductor element, method for fabricating the same, and semiconductor device including the same낮은 일함수의 탄화에르븀(란탄족) 게이트 전극을 갖는 반도체 소자를 제작하는 방법
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 조병진 | ko |
| dc.contributor.author | 안현준 | ko |
| dc.contributor.author | 문정민 | ko |
| dc.date.accessioned | 2017-12-20T02:14:22Z | - |
| dc.date.available | 2017-12-20T02:14:22Z | - |
| dc.date.issued | 2016-09-20 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/230434 | - |
| dc.description.abstract | A semiconductor element includes: a substrate; a gate dielectric layer formed over the substrate; a flat band voltage adjusting layer formed over the gate dielectric layer; and an intermediate layer formed between the gate dielectric layer and the flat band voltage adjusting layer. A negative flat band voltage generated at the intermediate layer and a positive flat band voltage generated between the substrate and the gate dielectric layer may offset each other. | - |
| dc.title | Semiconductor element, method for fabricating the same, and semiconductor device including the same | - |
| dc.title.alternative | 낮은 일함수의 탄화에르븀(란탄족) 게이트 전극을 갖는 반도체 소자를 제작하는 방법 | - |
| dc.type | Patent | - |
| dc.type.rims | PAT | - |
| dc.contributor.localauthor | 조병진 | - |
| dc.contributor.nonIdAuthor | 안현준 | - |
| dc.contributor.nonIdAuthor | 문정민 | - |
| dc.contributor.assignee | KAIST | - |
| dc.identifier.iprsType | 특허 | - |
| dc.identifier.patentApplicationNumber | 14828168 | - |
| dc.identifier.patentRegistrationNumber | 9450064 | - |
| dc.date.application | 2015-08-17 | - |
| dc.date.registration | 2016-09-20 | - |
| dc.publisher.country | US | - |
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