12-bit 100kS/S SAR ADC with 3+9bit segmented CDAC architecture
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 이희철 | ko |
| dc.contributor.author | 김태효 | ko |
| dc.date.accessioned | 2017-12-05T02:33:38Z | - |
| dc.date.available | 2017-12-05T02:33:38Z | - |
| dc.date.created | 2017-11-29 | - |
| dc.date.issued | 2017-06-29 | - |
| dc.identifier.citation | IDEC SoC Congress Chip Design Contest (ISC) | - |
| dc.identifier.uri | http://hdl.handle.net/10203/227679 | - |
| dc.language | English | - |
| dc.publisher | 반도체설계교육센터 (IDEC) | - |
| dc.title | 12-bit 100kS/S SAR ADC with 3+9bit segmented CDAC architecture | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | IDEC SoC Congress Chip Design Contest (ISC) | - |
| dc.identifier.conferencecountry | KO | - |
| dc.identifier.conferencelocation | KAIST KI빌딩 | - |
| dc.contributor.localauthor | 이희철 | - |
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