DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Taeho | ko |
dc.contributor.author | Kim, Yong Hun | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2017-12-05T01:53:11Z | - |
dc.date.available | 2017-12-05T01:53:11Z | - |
dc.date.created | 2017-04-04 | - |
dc.date.created | 2017-04-04 | - |
dc.date.created | 2017-04-04 | - |
dc.date.issued | 2017-01 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.380 - 384 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/227493 | - |
dc.description.abstract | A digital clock and data recovery (CDR) is presented, which employs a low supply sensitivity scheme for a digitally controlled oscillator (DCO). A coupling network comprising capacitors, resistors, and coupling buffers enhances the supply variation immunity of the DCO and mitigates the jitter performance degradation. A supply variation-dependent bias generator produces the corresponding bias voltage to alleviate the supply variation with minimal area and power penalty. The proposed scheme improves 29.3 ps of peak-to-peak jitter and 11.5 dB of spur level, at 6 and 5 MHz 50 mV(pp) sinusoidal supply noise tone, respectively. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER < 10(-12) for PRBS 31 and consumes 15.4 mW. The CDR occupies an active die area of 0.075 mm(2). | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network | - |
dc.type | Article | - |
dc.identifier.wosid | 000394591600032 | - |
dc.identifier.scopusid | 2-s2.0-84971474344 | - |
dc.type.rims | ART | - |
dc.citation.volume | 25 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 380 | - |
dc.citation.endingpage | 384 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2016.2566927 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Coupling network | - |
dc.subject.keywordAuthor | digital clock and data recovery (CDR) | - |
dc.subject.keywordAuthor | digitally controlled oscillator (DCO) | - |
dc.subject.keywordAuthor | highspeed serial link | - |
dc.subject.keywordAuthor | supply noise compensation | - |
dc.subject.keywordAuthor | supply variation-dependent bias generator (SDBG) | - |
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