DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Hyunik | ko |
dc.contributor.author | Kim, Yongjo | ko |
dc.contributor.author | Kim, Taeik | ko |
dc.contributor.author | Ko, Hyung-Jong | ko |
dc.contributor.author | Cho, Seonghwan | ko |
dc.date.accessioned | 2017-11-20T08:24:50Z | - |
dc.date.available | 2017-11-20T08:24:50Z | - |
dc.date.created | 2017-11-14 | - |
dc.date.created | 2017-11-14 | - |
dc.date.issued | 2017-11 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.11, pp.2934 - 2946 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/227045 | - |
dc.description.abstract | In this paper, we propose a low-jitter low-power digital multiplying delay-locked loop (MDLL) with a self-calibrated double reference injection scheme. To reduce jitter, the noisy edge of the oscillator is replaced by both the rising and falling edges of the clean reference, which results in 6-dB reduction in phase noise compared with a conventional single-edge injection MDLL. Reference spur caused by a frequency error of the oscillator, duty-cycle error of the reference, and circuit imperfection, such as offset and mismatch, is removed by employing three background feedback loops with a shared analog pulsewidth comparator. Implemented in 28-nm CMOS, the proposed digital MDLL generates 2.4-GHz clock and achieves a spur of -51.4 dBc and an rms jitter of 699 fs(rms) while consuming 1.5 mW from 1-V supply. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | PHASE-NOISE | - |
dc.subject | CHARGE-PUMP | - |
dc.subject | PLL | - |
dc.subject | CMOS | - |
dc.title | A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique | - |
dc.type | Article | - |
dc.identifier.wosid | 000413941800011 | - |
dc.identifier.scopusid | 2-s2.0-85030230362 | - |
dc.type.rims | ART | - |
dc.citation.volume | 52 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 2934 | - |
dc.citation.endingpage | 2946 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2017.2734910 | - |
dc.contributor.localauthor | Cho, Seonghwan | - |
dc.contributor.nonIdAuthor | Kim, Hyunik | - |
dc.contributor.nonIdAuthor | Kim, Taeik | - |
dc.contributor.nonIdAuthor | Ko, Hyung-Jong | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Double injection | - |
dc.subject.keywordAuthor | duty-cycle corrector (DCC) | - |
dc.subject.keywordAuthor | injection-locked oscillator | - |
dc.subject.keywordAuthor | multiplying delay-locked loop (MDLL) | - |
dc.subject.keywordAuthor | offset cancellation | - |
dc.subject.keywordAuthor | pulsewidth comparator (PWC) | - |
dc.subject.keywordAuthor | spur reduction | - |
dc.subject.keywordAuthor | time-to-voltage converter (TVC) | - |
dc.subject.keywordPlus | PHASE-NOISE | - |
dc.subject.keywordPlus | CHARGE-PUMP | - |
dc.subject.keywordPlus | PLL | - |
dc.subject.keywordPlus | CMOS | - |
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