A Two-step 5b Logarithmic ADC with Minimum Step-size of 0.1% Full-scale for MLC Phase-Change Memory Readout
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kwon, JW | ko |
| dc.contributor.author | Jin, DH | ko |
| dc.contributor.author | Kim, HJ | ko |
| dc.contributor.author | Hwang, SI | ko |
| dc.contributor.author | Shin, MC | ko |
| dc.contributor.author | Kang, JH | ko |
| dc.contributor.author | Ryu, Seung-Tak | ko |
| dc.date.accessioned | 2017-10-23T01:37:46Z | - |
| dc.date.available | 2017-10-23T01:37:46Z | - |
| dc.date.created | 2014-11-26 | - |
| dc.date.created | 2014-11-26 | - |
| dc.date.created | 2014-11-26 | - |
| dc.date.issued | 2014-09-17 | - |
| dc.identifier.citation | Custom Integrated Circuits Conference(CICC) | - |
| dc.identifier.uri | http://hdl.handle.net/10203/226338 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A Two-step 5b Logarithmic ADC with Minimum Step-size of 0.1% Full-scale for MLC Phase-Change Memory Readout | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000349122300056 | - |
| dc.identifier.scopusid | 2-s2.0-84928138001 | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | Custom Integrated Circuits Conference(CICC) | - |
| dc.identifier.conferencecountry | US | - |
| dc.identifier.conferencelocation | DoubleTree Hotel, San Jose, CA | - |
| dc.contributor.localauthor | Ryu, Seung-Tak | - |
| dc.contributor.nonIdAuthor | Kwon, JW | - |
| dc.contributor.nonIdAuthor | Jin, DH | - |
| dc.contributor.nonIdAuthor | Kim, HJ | - |
| dc.contributor.nonIdAuthor | Hwang, SI | - |
| dc.contributor.nonIdAuthor | Shin, MC | - |
| dc.contributor.nonIdAuthor | Kang, JH | - |
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