DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Hyeon-June | ko |
dc.contributor.author | Hwang, Sun-Il | ko |
dc.contributor.author | Chung, Jaehyun | ko |
dc.contributor.author | Park, Jong-Ho | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2017-09-25T06:02:17Z | - |
dc.date.available | 2017-09-25T06:02:17Z | - |
dc.date.created | 2017-09-18 | - |
dc.date.created | 2017-09-18 | - |
dc.date.created | 2017-09-18 | - |
dc.date.issued | 2017-09 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.9, pp.2488 - 2497 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/226130 | - |
dc.description.abstract | This paper presents a CMOS image sensor (CIS) that extracts a multi-level edge image as well as a human-friendly normal image in a real time from conventional pixels for machine-vision applications, utilizing a proposed speed/power-efficient dual-mode successive-approximation register analog-to-digital converter (SAR ADC). The proposed readout scheme operates in two modes, fine step SAR (FS-SAR) mode and coarse-step single-slope (CS-SS) mode, depending on the difference (Delta) between a chosen pixel and the previous pixel. If a chosen pixel is at a boundary of an object with a large Delta from the previous pixel, the readout ADC works in the CS-SS mode to readout the edge strength (ES), while the FS-SAR mode is applied for other pixels. By displaying the ES, a multi-level edge image can be obtained in a real time along with a normal image with no hardware/time overhead. By saving the MSBs conversion cycles regardless of Delta, the proposed dual-mode readout scheme enhances the readout speed and reduces power consumption. A prototype QQVGA CIS with 10-bit SAR ADCs was fabricated in a 0.18-mu m 1P4M CMOS image sensor process with a 4.9-mu m pixel pitch. With a maximum pixel rate of 61.4 Mp/s, the prototype demonstrated figure of merits of 70 pJ/pixel/frame, 0.35 e(-) . nJ, and 0.34 e(-) . pJ/step. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction | - |
dc.type | Article | - |
dc.identifier.wosid | 000408338600022 | - |
dc.identifier.scopusid | 2-s2.0-85028695603 | - |
dc.type.rims | ART | - |
dc.citation.volume | 52 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 2488 | - |
dc.citation.endingpage | 2497 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2017.2718665 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Park, Jong-Ho | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | CMOS image sensor (CIS) | - |
dc.subject.keywordAuthor | delta (Delta) | - |
dc.subject.keywordAuthor | dual-mode readout scheme | - |
dc.subject.keywordAuthor | multi-column-parallel (MCP) | - |
dc.subject.keywordAuthor | multi-level edge image | - |
dc.subject.keywordAuthor | real-time edge image | - |
dc.subject.keywordAuthor | successive-approximation register analog-to-digital converter (SAR ADC) | - |
dc.subject.keywordPlus | DIGITAL ERROR-CORRECTION | - |
dc.subject.keywordPlus | SAR ADC | - |
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