DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jeong, Gwanghyeon | ko |
dc.contributor.author | Joo, Taehwan | ko |
dc.contributor.author | Hong, Songcheol | ko |
dc.date.accessioned | 2017-07-18T05:42:55Z | - |
dc.date.available | 2017-07-18T05:42:55Z | - |
dc.date.created | 2017-07-03 | - |
dc.date.created | 2017-07-03 | - |
dc.date.issued | 2017-06 | - |
dc.identifier.citation | IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.27, no.6, pp.596 - 598 | - |
dc.identifier.issn | 1531-1309 | - |
dc.identifier.uri | http://hdl.handle.net/10203/224785 | - |
dc.description.abstract | This letter proposes a highly efficient CMOS linear power amplifier (PA) with cascode-cascade configuration. The proposed configuration improves AM-PM distortion through a capacitance variation compensation of the input capacitance of a common-gate stage in the main amplifier and a common-source stage of an auxiliary amplifier. In addition, the current consumption in the low-power region is significantly reduced structurally because the auxiliary amplifier is turned off. The PA is implemented in 0.18-mu m CMOS process with an output combining network in printed circuit board. It provides an average power of 24.5 dBm with a PAE of 45.6% for a long-term-evolution 10-MHz up-link signal with the ACLR(E)-UTRA of -30 dBc at 2 GHz. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | LTE | - |
dc.title | A Highly Linear and Efficient CMOS Power Amplifier With Cascode-Cascade Configuration | - |
dc.type | Article | - |
dc.identifier.wosid | 000403292100022 | - |
dc.identifier.scopusid | 2-s2.0-85019907877 | - |
dc.type.rims | ART | - |
dc.citation.volume | 27 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 596 | - |
dc.citation.endingpage | 598 | - |
dc.citation.publicationname | IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | - |
dc.identifier.doi | 10.1109/LMWC.2017.2701327 | - |
dc.contributor.localauthor | Hong, Songcheol | - |
dc.contributor.nonIdAuthor | Joo, Taehwan | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | AM-AM | - |
dc.subject.keywordAuthor | AM-PM | - |
dc.subject.keywordAuthor | capacitance compensation | - |
dc.subject.keywordAuthor | cascode-cascade configuration | - |
dc.subject.keywordAuthor | CMOS power amplifier (PA) | - |
dc.subject.keywordAuthor | long-term-evolution (LTE) | - |
dc.subject.keywordPlus | LTE | - |
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