DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chang, Dong-Jin | ko |
dc.contributor.author | Kim, Wan | ko |
dc.contributor.author | Seo, Min-Jae | ko |
dc.contributor.author | Hong, Hyeok-Ki | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2017-03-30T09:18:55Z | - |
dc.date.available | 2017-03-30T09:18:55Z | - |
dc.date.created | 2017-03-29 | - |
dc.date.created | 2017-03-29 | - |
dc.date.issued | 2017-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.2, pp.322 - 332 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/222727 | - |
dc.description.abstract | This paper proposes a linearity calibration algorithm of a capacitive digital-to-analog converter (CDAC) for successive approximation register (SAR) analog-to-digital converters (ADCs) based on a normalized-full-scale of the DAC. Since the capacitor weight errors are represented as the difference between the real and ideal weights with respect to the normalized-full-scale, the calibrated digital representation of CDAC does not have gain error. A model of a 14-bit-format SAR ADC with a segmented CDAC by a bridge capacitor is simulated to demonstrate the performance of the proposed calibration algorithm. The effective number of bits (ENOB) and spurious-free dynamic range (SFDR) of the 14-bit-format ADC model are improved to 13.2 bits and 94.0 dB from 8.4 bits and 54.8 dB, respectively, at a standard deviation of a unit capacitor of 2%. The gain-error-free characteristic of the proposed linearity calibration algorithm is verified with a 2-channel time-interleaved (TI) SAR ADC model. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | NM CMOS | - |
dc.title | Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC | - |
dc.type | Article | - |
dc.identifier.wosid | 000395487900007 | - |
dc.identifier.scopusid | 2-s2.0-85010006397 | - |
dc.type.rims | ART | - |
dc.citation.volume | 64 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 322 | - |
dc.citation.endingpage | 332 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2016.2612692 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Capacitor DAC | - |
dc.subject.keywordAuthor | CDAC linearity calibration | - |
dc.subject.keywordAuthor | digital calibration | - |
dc.subject.keywordAuthor | full-scale referring calibration | - |
dc.subject.keywordAuthor | SAR ADC | - |
dc.subject.keywordAuthor | time-interleaved ADC. | - |
dc.subject.keywordPlus | NM CMOS | - |
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