Thermal resistance effects of packages on LDMOS power amplifier transistor

Abstract

In this thesis, we studied the effects of package contact thermal resistance on LDMOS power amplifier transistor by combining thermal analysis and circuit analysis. Thermal analysis of the LDMOS power amplifier transistor has been performed by observing the junction temperature changes as the package contact area due to voids. Also, relationships of package contact thermal resistance and power amplifier transistor performance like mobility, threshold voltage, and drain current have been derived by results of thermal analysis and equivalent circuit model. Finally, it has been observed that the performance of the power amplifier transistor worsens as package contact thermal resistance has been increased by RF simulation. It has been found that the amount of change in performance degradation of the test board has been nearly doubled when the amount of change in package thermal resistance to be doubled.