DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Moon, Jaekyun | - |
dc.contributor.advisor | 문재균 | - |
dc.contributor.author | Kang, Soonyoung | - |
dc.contributor.author | 강순영 | - |
dc.date.accessioned | 2017-03-29T02:47:59Z | - |
dc.date.available | 2017-03-29T02:47:59Z | - |
dc.date.issued | 2016 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=663165&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/222305 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2016.8 ,[iii, 46 p. :] | - |
dc.description.abstract | Trapping sets strongly degrade performance of low-density parity-check (LDPC) codes in the low error rate region. This creates significant difficulties to the deployment of LDPC codes to low-error-rate applications like storage and wireless systems with no or limited retransmission options. This dissertation proposes a novel technique for breaking trapping sets based on collaborative decoding that utilizes two different decoding modes. While the main decoding mode executes message passing based on the original parity check matrix of the corresponding LDPC code, the sub-decoding mode operates on a modified parity check matrix formed by removing a portion of check nodes in the factor graph representation of the given code. The modified parity check matrix is designed to promote a passing of correct information into erroneous variable nodes in the trapping set. Theoretical properties of the proposed trapping-set-breaking technique have been established based on the notion of the improved separation for the trapped variable nodes. Simulation results show that the proposed collaborative LDPC decoding effectively breaks dominant trapping sets of various known types of regular and irregular LDPC codes. This dissertation also provides a hardware implementation of a bi-mode LDPC decoder based on the collaborative decoding. Implementation of the bi-mode collaborative decoder only requires a small number of additional hardware components to the conventional single decoder. For a (2048,1723) regular code, the bi-mode decoder requires 4% and less than 1% overhead for memory and logic, respectively. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | low-density parity-check codes | - |
dc.subject | error floor | - |
dc.subject | trapping set | - |
dc.subject | collaborative decoding | - |
dc.subject | iterative decoder architecture | - |
dc.subject | 저밀도 패리티 체크 부호 | - |
dc.subject | 오류 마루 | - |
dc.subject | 트랩핑셋 | - |
dc.subject | 협력 디코딩 | - |
dc.subject | 반복 복호기 구조 | - |
dc.title | Collaborative decoding algorithm and architecture for improved low error rate performance of LDPC codes | - |
dc.title.alternative | 저밀도 패리티 체크 부호의 낮은 오류율 성능 향상을 위한 협력 복호 알고리즘 및 하드웨어 구조 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
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