Low-noise time-interleaved SAR ADC for low-supply voltage applications

Abstract

With growing demand for ultra-low-power applications, low-supply-voltage circuit design has been an attractive and plausible option for low-power system designs. However, high-performance analog/mixed-signal circuit designs become difficult under a low supply voltage because of the degraded operational speed, signal-to-noise ratio (SNR) degradation due to the reduced signal power, and the increased clock jitter. In order to overcome these limitations, an asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC is proposed as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high frequency operation while it generates a low-power-but-low-quality clock for low frequency operation. With the dual-mode clock generator enabled, a prototype 65nm CMOS 0.6V 12b 10MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24LSB and 0.45LSB, respectively. The FoM is 6.2fJ/conversion-step with a power consumption of $83 \mu W$ . The ADC operates under the lowest supply voltage of 0.6V among comparable designs with ENOBs over 10 and conversion rates over 1MS/s.