(A) new resistance model for a schottky barrier diode in CMOS including n-well thickness effect

Abstract

Schottky barrier diode(SBD) is a two-terminal device that can be used in very high frequency band, especially in terahertz region. CMOS technology is good in terms of high integrability and low cost. CMOS SBD can be a solution to approach to terahertz region with CMOS technology. In this thesis, an accurate analysis for CMOS SBDs is done. Especially, a new resistance model for CMOS SBDs is proposed. The proposed model includes the n-well thickness as a variable to explain the operational behavior of a planar SBD. The model is verified using the simulation methodology SILVACO. For verification of the analyzed model and the SILVACO simulation results, SBD patterns are fabricated using a $0.13$\mu m$ CMOS process. It is demonstrated that the model and simulation results are consistent with measurement results of fabricated SBD. The tendency series resistance, junction capacitance, and cutoff frequency for various anode size is also discussed from measurement result of fabricated SBD.