DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Yoo, Hyung-Joun | - |
dc.contributor.advisor | 유형준 | - |
dc.contributor.author | Suh, Ji-Hoon | - |
dc.contributor.author | 서지훈 | - |
dc.date.accessioned | 2017-03-29T02:38:26Z | - |
dc.date.available | 2017-03-29T02:38:26Z | - |
dc.date.issued | 2016 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=649570&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/221767 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2016.2 ,[v, 42 p. :] | - |
dc.description.abstract | For multiparameter sensor environment, where various types of sensors are used such as implantable devices and mobile health care, a versatile version of analog front-end is suggested. The proposed analog front-end adopts capacitive, resistive, and voltage type interfaces especially targeted for microsystems. In order for the interface circuits to have linear conversion characteristic and large conversion gain, the most attractive topologies are adopted: switched capacitor integrator, current source, and fully differential amplifier. Each interface has an excellent linearity ($R^{2}$ > 0.999) with respect to the variation of C, R, and V. For each interface, the maximum conversion gains at output are: 194.56 mV/fF for the ca-pacitive interface, $6.26 V/k \Omega$ for the resistive interface, and 236 V/V for the voltage ampli-fier. Besides the basic interfaces, the analog front-end is designed to cancel 1/f noise and offsets. On simulation, the AFE suppresses 1/f noise at 10 Hz by 30 dB for buffers and 44 dB for fully differential amplifiers based on correlated double sampling scheme. Offset is canceled with two separate schemes: signal level shifting and amplifier balancing. Based on the schemes, offset voltage is suppressed with 0.6 mV resolution | - |
dc.description.abstract | this prevents amplifier from saturating even at the maximum gain and ensures pure sensor signal to have large room for swing. The AFE operates at 2.5 V supply, and is designed using TSMC $0.25 \mu m$ CMOS technology. Overall power consumption is no more than 4 mW. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | microsystems | - |
dc.subject | multiparameter sensor interface | - |
dc.subject | correlated double sampling | - |
dc.subject | offset cancellation | - |
dc.subject | switched-capacitor circuits | - |
dc.subject | 마이크로 시스템 | - |
dc.subject | 멀티 파라미터 센서 인퍼테이스 | - |
dc.subject | CDS | - |
dc.subject | 오프셋 저감 | - |
dc.subject | 스위치-캐패시터 회로 | - |
dc.title | Multiparameter sensor interface circuit for microsystems | - |
dc.title.alternative | 마이크로 시스템에 적용 가능한 멀티 파라미터 센서 인터페이스 회로 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
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