(A) power efficient hybrid PAM4 transmitter with supply noise suppression loop

Abstract

PAM4 transceiver is able to communicate 2-bit information in 1UI pulse. However, there is weak point that PAM4 has one third of eye-height than NRZ from 4 different levels of the signal. This signal characteristic cuts down -9.5dB SNR. Consequently, there are several attempts to enlarge the differential peak-to-peak swing of transmitter for compensating signal characteristic. In this paper, wide output swing 3-tap FFE transmitter is pro-posed to support high speed PAM4 signal with supply noise suppression loop. This proposed circuit achieves 1.33V peak-to-peak differential output swing with only 1V supply and with-out any high-voltage devices. Hybrid driver architecture based on SST saves huge power consumption and to secure wide swing range. For better PSRR and jitter performance, there is replica driver. It includes supply noise suppression loop can compensate the noise from supply. Loops are tied to supply-dependent reference voltage built from the noiseless electrical ground. Additionally, the 3-tap feed-forward equalizer is implemented with only current-mode driver for reduce the pre-driver load of each FIR tap. This architecture can avoid the power/area waste from bulky pre-driver. The proposed transmitter is implemented in 40nm CMOS process. It can operate in 28/56Gbps NRZ/PAM4 dual-mode with 3-tap feed-forward equalizer. Supply noise suppression loop can reduce PSRR under -10dB up to 10MHz. FFE can boost 3.2dB of output signal in terms of NRZ. The total power consumption of transmitter is 23.16mW. The FoM of this architecture is 0.42pJ/bit. The area of total circuit is $0.013mm^{2}$.