TID and SEE hardened n-MOSFET layout on a bulk silicon substrate which combines a DGA n-MOSFET and a guard drain

Abstract

A new n-MOSFET layout on a bulk silicon substrate proposed for TID and SEE radiation tolerance combing a DGA n-MOSFET and a guard drain. The proposed n-MOSFET layout consists of a p+ and a p-active layer on the source-to-drain sidewall to prevent the development of a leakage path between the source and the drain, a dummy gate on the side drain/source to avoid the development of a leakage path between two MOSFETs, and a guard drain on the side dummy gate to reduce the SEE effect. The proposed n-MOSFET layout was found to eliminate all radiation-induced leakage current paths and to reduce SEE pulse to 35.36% in comparison with the conventional n-MOSFET. The simulation results demonstrated that the proposed n-MOSFET structure on the bulk silicon substrate performs well even when the fixed charge density increases and energetic protons are injected. These results confirm that the proposed n-MOSFET on the bulk silicon substrate is radiation-tolerant.