DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Hyun-Jeong | ko |
dc.contributor.author | Kim, Hyung-Soo | ko |
dc.contributor.author | Pak, Jun-So | ko |
dc.contributor.author | Yoon, Chang-Wook | ko |
dc.contributor.author | Koo, Kyoung-Choul | ko |
dc.contributor.author | Kim, Joung-Ho | ko |
dc.date.accessioned | 2011-01-26T08:53:51Z | - |
dc.date.available | 2011-01-26T08:53:51Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2008-04 | - |
dc.identifier.citation | IEICE TRANSACTIONS ON ELECTRONICS, v.E91C, pp.595 - 606 | - |
dc.identifier.issn | 0916-8524 | - |
dc.identifier.uri | http://hdl.handle.net/10203/21833 | - |
dc.description.abstract | In this paper, we present and verify a new chip-package co-modeling and simulation approach for a low-noise chip-package hierarchical power distribution network (PDN) design. It is based on a hierarchical modeling to combine distributed circuit models at both chip-level PDN and package-level PDN. In particular, it includes all on- and off-chip parasitic circuit elements in the hierarchical PDN with a special consideration on on-chip decoupling capacitor design and placement inside chip. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of Z11 and Z21 PDN impedance measurements with a frequency range from 1 MHz to 3 GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the chip-level PDN and the package-level PDN. Furthermore, we can precisely anticipate PDN resonance frequencies, noise generation sources, and noise propagation paths through the multiple levels in the hierarchical PDN. | - |
dc.description.sponsorship | This work was supported by the IT R&D program of MIC/IITA. [2005-S-118-02, Development of High Performance and Smallest SiP Technology] | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.subject | THROUGH-HOLE SIGNAL | - |
dc.subject | RADIATED EMISSIONS | - |
dc.subject | SWITCHING NOISE | - |
dc.subject | CAPACITOR | - |
dc.subject | DESIGN | - |
dc.subject | SUPPRESSION | - |
dc.subject | METHODOLOGY | - |
dc.subject | PCBS | - |
dc.title | Co-modeling, experimental verification, and analysis of chip-package hierarchical power distribution network | - |
dc.type | Article | - |
dc.identifier.wosid | 000255648200023 | - |
dc.identifier.scopusid | 2-s2.0-77952741629 | - |
dc.type.rims | ART | - |
dc.citation.volume | E91C | - |
dc.citation.beginningpage | 595 | - |
dc.citation.endingpage | 606 | - |
dc.citation.publicationname | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.identifier.doi | 10.1093/ietele/e91-c.4.595 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Kim, Joung-Ho | - |
dc.contributor.nonIdAuthor | Park, Hyun-Jeong | - |
dc.contributor.nonIdAuthor | Kim, Hyung-Soo | - |
dc.contributor.nonIdAuthor | Pak, Jun-So | - |
dc.contributor.nonIdAuthor | Yoon, Chang-Wook | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | co-modeling | - |
dc.subject.keywordAuthor | hierarchical power distribution network (PDN) | - |
dc.subject.keywordAuthor | chip and package | - |
dc.subject.keywordPlus | THROUGH-HOLE SIGNAL | - |
dc.subject.keywordPlus | RADIATED EMISSIONS | - |
dc.subject.keywordPlus | SWITCHING NOISE | - |
dc.subject.keywordPlus | CAPACITOR | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | SUPPRESSION | - |
dc.subject.keywordPlus | METHODOLOGY | - |
dc.subject.keywordPlus | PCBS | - |
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