DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Joon Yeong | ko |
dc.contributor.author | Han, Kwangseok | ko |
dc.contributor.author | Yoon, Taehun | ko |
dc.contributor.author | Kim, Taeho | ko |
dc.contributor.author | Lee, Sang-Eun | ko |
dc.contributor.author | Lee, Jeong-Sup | ko |
dc.contributor.author | Park, Jinho | ko |
dc.contributor.author | Bae, Hyeon-Min | ko |
dc.date.accessioned | 2016-11-30T08:34:11Z | - |
dc.date.available | 2016-11-30T08:34:11Z | - |
dc.date.created | 2016-11-16 | - |
dc.date.created | 2016-11-16 | - |
dc.date.created | 2016-11-16 | - |
dc.date.issued | 2016-10 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.10, pp.2475 - 2484 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/214239 | - |
dc.description.abstract | A phase interpolator (PI)-based 10 x10 Gb/s bootstrap transceiver for referenceless and lane-independent operation is presented. PI output clock signals phase locked to the input data are used as reference clock signals for frequency locking the voltage-controlled oscillator (VCO). The VCO clock signal is then redistributed to the PIs, triggering the bootstrapping between the VCO and the PIs. All lanes operate independently as in VCO-based parallel referenceless designs while saving power and area. The measured recovered-data jitter in each lane is 0.93 ps(rms) and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology. The test chip achieves figure-of-merits (mW/Gbps) of 2.03 and 2.13 for the receiver and the transmitter, respectively | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DATA RECOVERY CIRCUIT | - |
dc.subject | FREQUENCY ACQUISITION | - |
dc.subject | CLOCK | - |
dc.title | A Power-and-Area Efficient 10 x 10 Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation | - |
dc.type | Article | - |
dc.identifier.wosid | 000385240200025 | - |
dc.identifier.scopusid | 2-s2.0-85027399253 | - |
dc.type.rims | ART | - |
dc.citation.volume | 51 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 2475 | - |
dc.citation.endingpage | 2484 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2016.2590550 | - |
dc.contributor.localauthor | Bae, Hyeon-Min | - |
dc.contributor.nonIdAuthor | Kim, Taeho | - |
dc.contributor.nonIdAuthor | Lee, Sang-Eun | - |
dc.contributor.nonIdAuthor | Lee, Jeong-Sup | - |
dc.contributor.nonIdAuthor | Park, Jinho | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Bootstrap CDR | - |
dc.subject.keywordAuthor | lane-independent parallel transceiver | - |
dc.subject.keywordAuthor | low power transceiver | - |
dc.subject.keywordAuthor | phase interpolator-based clock and data recovery (CDR) | - |
dc.subject.keywordAuthor | referenceless frequency acquisition | - |
dc.subject.keywordPlus | DATA RECOVERY CIRCUIT | - |
dc.subject.keywordPlus | FREQUENCY ACQUISITION | - |
dc.subject.keywordPlus | CLOCK | - |
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