DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Wan | ko |
dc.contributor.author | Hong, Hyeok-Ki | ko |
dc.contributor.author | Roh, Yi-Ju | ko |
dc.contributor.author | Kang, Hyun-Wook | ko |
dc.contributor.author | Hwang, Sun-Il | ko |
dc.contributor.author | Jo, Dong Shin | ko |
dc.contributor.author | Chang, Dong-Jin | ko |
dc.contributor.author | Seo, Min-Jae | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2016-11-09T02:46:59Z | - |
dc.date.available | 2016-11-09T02:46:59Z | - |
dc.date.created | 2016-10-10 | - |
dc.date.created | 2016-10-10 | - |
dc.date.issued | 2016-08 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.8, pp.1826 - 1839 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/213563 | - |
dc.description.abstract | This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-but-low-quality clock for low-frequency operation. With the dual-mode clock generator enabled, a prototype 65 nm CMOS 0.6 V 12 b 10 MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24 LSB and 0.45 LSB, respectively. The FoM is 6.2 fJ/conversion-step with a power consumption of 83 mu W. The ADC operates under the lowest supply voltage of 0.6 V among comparable designs with ENOBs over 10 and conversion rates over 1 MS/s | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | NM CMOS | - |
dc.subject | REDUCTION | - |
dc.title | A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI- SAR) ADC | - |
dc.type | Article | - |
dc.identifier.wosid | 000382169400009 | - |
dc.identifier.scopusid | 2-s2.0-84973926843 | - |
dc.type.rims | ART | - |
dc.citation.volume | 51 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 1826 | - |
dc.citation.endingpage | 1839 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2016.2563780 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Asynchronous SAR ADC | - |
dc.subject.keywordAuthor | gain-boosting dynamic comparator | - |
dc.subject.keywordAuthor | low voltage | - |
dc.subject.keywordAuthor | low-jitter clock | - |
dc.subject.keywordAuthor | low-noise comparator | - |
dc.subject.keywordAuthor | SAR-assisted time-interleaved SAR (SATI-SAR) | - |
dc.subject.keywordPlus | NM CMOS | - |
dc.subject.keywordPlus | REDUCTION | - |
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